The present invention relates to a flash memory device a program method thereof, and more particularly, to a flash memory device and program method capable of increasing a programming speed.
Generally, a flash memory device includes an insulating layer, a floating gate, a dielectric layer and a control gate, which are laminated on a semiconductor substrate. The floating gate is used as a charge storing layer, and the details thereof will be described.
When a program voltage is applied to a control gate through a selected word line, a Fowler-Nordheim (F-N) tunneling phenomenon is produced between a semiconductor substrate and a floating gate, and thus electrons flow into the floating gate from the semiconductor substrate to perform a program operation.
A floating gate storing electrons becomes a programmed cell to be higher in a voltage than a threshold voltage of an erase, and thus the programmed cell can be distinguished from the erase cell by reading this distribution difference of a threshold voltage.
A flash memory device has two states, for example, an erase state or a programmed state, and the memory device driven in one erase state and one programmed state refers to as a single level chip (“SLC”). In the other hands, a programming method of each memory cell in multi-level to store much more data than the single line chip SLC has been developed, which is referred to as a multi level chip (“MLC”). The multi line chip MLC is operated in a way of defining each data state which is different each other in respective distribution intervals of the threshold voltage. More details thereof will be described.
For example, when data is stored on the multi line chip MLC, the states that one memory cell may have can be sorted into an erase state, a PV1 state, a PV2 state and PV3 state. Here, assuming that the PV1 state is the programmed state with the lowest interval among the programmed threshold voltage intervals, the PV2 state is higher in threshold distributions than the PV1 state, and the PV3 state is higher than the PV2 state. Like this, with respect to the respective threshold voltage intervals, data of multi bit (i.e., 11, 01, 00 and 01) may be defined in sequence. In the following, a description thereof will be made with reference to FIG. 1.
FIGS. 1A to 1D show a conventional program method of a flash memory device. Each threshold voltage interval that a memory cell may have sorted into an erase state, a PV1 state, a PV2 state and PV3 state, and data value of 2 bit (multi bit) is defined to each state. A lower bit of data values of 2 bit refers to as a low page, and a higher bit refers to as a high page. A program operation of the low page refers to as a low page program “LSB program”, and a program operation of the high page refers to as a high page program “MSB program”.
The programming sequence of the multi line chip MLC will be described.
Firstly, in memory cell array configured by a unit of block, all of the memory cells of the selected blocks are erased (FIG. 1A). Subsequently, a low page program LSB operation is performed.
In the low page program LSB operation, among memory cells of erase states, a ground voltage is applied to the bit lines of the selected memory cells and a source voltage is applied to the bit lines of the non-selected memory cells. The low page program LSB operation is performed in such a way that a program voltage is applied to the selected word lines and a pass voltage is applied to the non-selected word lines. Accordingly, through these procedures of the low page program LSB operation, the selected memory cells of erase states become PV1 state (FIG. 1B).
The high page program MSB operations may be sorted into a first high page program MSB and a second high page program MSB.
The first high page program MSB operation is an operation for programming the selected memory cells into the PV2 state. To program the erased memory cells into the PV2 state, the selected memory cells are LSB-programmed to the PV1 state from the erase state and then the first MSB program is performed thereto to make the selected memory cells be in PV2 state (FIG. 1C).
The second high page program MSB operation is an operation for programming the selected memory cells into the PV3 state (FIG. 1D). The second high page program MSB is performed in such a way that among memory cells of erase states, a ground voltage is applied to the bit lines of the selected memory cells and a program voltage is applied to the word lines connected to the selected memory cells.
A program operation speed of the multi level chip MLC may be reduced since each program operation has to be performed to program cells from erase states to the respective programmed state (PV 1 state, PV2 state or PV3 state).